Search - verilog uart

[VHDL-FPGA-Verilog] ad706_test

Description: AD7606的FPGA驱动，AD7606与FPGA通过并行模式连接。FPGA可以将AD采集到的信号转换成电压信号通过串口输出，可通过PC机串口调试助手查看。实测可用(The drive program of AD7606 write by verilog. FPGA can convert the AD7606'sigal to volatage and send the converted signal to PC through uart.)
Platform: | Size: 14983168 | Author: Pgaf | Hits:

[VHDL-FPGA-Verilog] _uart_test2

Description: data transmitted from FPGA to PC using COM PORT version 2
Platform: | Size: 8192 | Author: anh92 | Hits:

[VHDL-FPGA-Verilog] 07_uart_test

Description: 黑金FPGA开发板实现串口Uart通信的verilog代码(Serial Uart communication)
Platform: | Size: 390144 | Author: 啊啊啊阿波 | Hits:

[VHDL-FPGA-Verilog] txd_interface

Description: 串口发送接口控制联合uart_txd_contrl实现(uart TXD Verilog)
Platform: | Size: 1024 | Author: 王峰 | Hits:

[VHDL-FPGA-Verilog] experiment_4_uart_communication

Description: 这是一个uart串口通信的代码，是基于ise运行的verilog语言，可以实现上位机和开发板的通信以及开发板显示数据并返回累加和的功能。( This is a serial code for uart communication is based on running ise verilog language, you can achieve PC and development board communications, and development boards to display the data and return the cumulative sum function.)
Platform: | Size: 2985984 | Author: michael lee | Hits:

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[VHDL-FPGA-Verilog] ad706_test

[VHDL-FPGA-Verilog] _uart_test2

[VHDL-FPGA-Verilog] 07_uart_test

[VHDL-FPGA-Verilog] txd_interface

[VHDL-FPGA-Verilog] experiment_4_uart_communication

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